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ltc3418 1 3418fb typical application description 8a, 4mhz, monolithic synchronous step-down regulator features applications n high ef? ciency: up to 95% n 8a output current n 2.25v to 5.5v input voltage range n low r ds(on) internal switch: 35m n tracking input to provide easy supply sequencing n programmable frequency: 300khz to 4mhz n 0.8v 1% reference allows low output voltage n quiescent current: 380a n selectable forced continuous/burst mode ? operation with adjustable burst clamp n synchronizable switching frequency n low dropout operation: 100% duty cycle n power good output voltage monitor n overtemperature protected n 38-lead low pro? le (0.75mm) thermally enhanced qfn (5mm 7mm) package n microprocessor, dsp and memory supplies n distributed 2.5v, 3.3v and 5v power systems n automotive applications n point of load regulation n notebook computers the ltc ? 3418 is a high ef? ciency, monolithic synchro- nous step-down dc/dc converter utilizing a constant frequency, current mode architecture. it operates from an input voltage range of 2.25v to 5.5v and provides a regulated output voltage from 0.8v to 5v while delivering u p t o 8 a o f o u t p u t c u r r e n t . t h e i n t e r n a l s y n c h r o n o u s p o w e r switch increases ef? ciency and eliminates the need for an external schottky diode. switching frequency is set by an external resistor or can be synchronized to an external clock. opti-loop ? compensation allows the transient response to be optimized over a wide range of loads and output capacitors. the ltc3418 can be con? gured for either burst mode operation or forced continuous operation. forced con- tinuous operation reduces noise and rf interference while burst mode operation provides high ef? ciency by reducing gate charge losses at light loads. in burst mode operation, external control of the burst clamp level allows the output voltage ripple to be adjusted according to the requirements of the application. a tracking input in the ltc3418 allows for proper sequencing with respect to another power supply. 2.5v/8a step-down regulator ef? ciency and power loss vs load current sv in track r t c in 47f 4 0.2h ltc3418 run/ss i th pgood sw pgnd sgnd sync/mode v fb 332 pv in 820pf 3418 ta01a 1000pf c out 100f 2 v out 2.5v 8a 4.32k 1.69k 30.1k 2.2m v in 2.8v to 5.5v 4.99k load current (a) 0.01 60 efficiency (%) power loss (mw) 80 100 0.1 1 10 3418 ta01b 40 50 70 90 30 20 1000 100000 100 10000 10 1 efficiency power loss v in = 3.3v v out = 2.5v l , lt, ltc and ltm are registered trademarks of linear technology corporation. burst mode and opti-loop are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 6724174.
ltc3418 2 3418fb pin configuration absolute maximum ratings electrical characteristics the l indicates speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 3.3v. (note 2) (note 1) input supply voltage ................................... C 0.3v to 6v i th , run/ss, v fb voltages ......................... C 0.3v to v in sync/mode voltages ................................ C 0.3v to v in track voltage ........................................... C 0.3v to v in sw voltage .................................. C 0.3v to (v in + 0.3v) operating temperature range (note 2) ...............................................C 40c to 85c junction temperature (note 5) ............................. 125c storage temperature range .................. C 65c to 125c symbol parameter conditions min typ max units v in input voltage range 2.25 5.5 v v fb regulated feedback voltage 0c t a 85c (note 3) l 0.792 0.784 0.800 0.800 0.808 0.816 v v i fb feedback input current 100 200 na v fb reference voltage line regulation v in = 2.5v to 5.5v (note 3) 0.04 0.2 %/v v loadreg output voltage load regulation measured in servo loop, v ith = 0.36v measured in servo loop, v ith = 0.84v l l 0.02 C0.02 0.2 C0.2 % % v track tracking voltage offset v track = 0.4v 15 mv tracking voltage range 00.8v 13 14 15 16 top view 39 uhf package 38-lead (7mm 5mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1 sw sw pv in pv in pgood r t run/ss sgnd pv in pv in sw sw sw sw pv in pv in sync/mode i th v fb sv in pv in pv in sw sw pgnd pgnd pgnd track pgnd pgnd pgnd pgnd pgnd pgnd v ref pgnd pgnd pgnd 23 22 21 20 9 10 11 12 t jmax = 125c, ja = 34c/w, jc = 1c/w exposed pad (pin 39) is pgnd, must be soldered to pcb order information lead free finish tape and reel part marking package description temperature range ltc3418euhf#pbf ltc3418euhf#trpbf 3418 38-lead (7mm 5mm) plastic qfn C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
ltc3418 3 3418fb electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v in = 3.3v. (note 2) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3418 is guaranteed to meet performance speci? cations from 0c to 85c. speci? cations over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 3: the ltc3418 is tested in a feedback loop that adjusts v fb to achieve a speci? ed error ampli? er output voltage (i th ). note 4: dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency. note 5: t j is calculated from the ambient temperature t a and power dissipation p d as follows: ltc3418: t j = t a + (p d )(34c/w) note 6: this parameter is guaranteed by design and characterization. symbol parameter conditions min typ max units i track track input current 100 200 na v pgood power good range 7.5 9 % r pgood power good resistance 100 150 i q input dc bias current active current shutdown (note 4) v fb = 0.7v, v ith = 1v v run = 0v 380 0.03 450 1.5 a a f osc switching frequency switching frequency range r osc = 69.8k (note 6) 0.88 0.3 11.12 4 mhz mhz f sync sync capture range (note 6) 0.3 4 mhz r pfet r ds(on) of p-channel fet i sw = 600ma 35 50 m r nfet r ds(on) of n-channel fet i sw = C 600ma 25 35 m i limit peak current limit 12 17 a v uvlo undervoltage lockout threshold 1.75 2 2.25 v v ref reference output 1.219 1.250 1.281 v i lsw sw leakage current v run = 0v, v in = 5.5v 0.1 1 a v run run threshold 0.5 0.65 0.8 v typical performance characteristics t a = 25c unless otherwise noted. switch on-resistance vs input voltage input voltage (v) 2.25 0 on-resistance (m) 5 15 20 25 4.25 45 3418 g02 10 3.25 2.75 4.75 3.75 5.25 30 pfet nfet 35 40 on-resistance vs temperature temperature (c) C40 0 on-resistance (m ) 5 15 20 25 50 35 0 40 60 3418 g03 10 40 45 30 pfet nfet C20 20 80 100 120 v in = 3.3v temperature ( c) ?40 ?20 reference voltage (v) 0.7980 0.7990 120 3418 g01 0.7970 0.7960 020 40 60 100 80 0.8000 0.7975 0.7985 0.7965 0.7995 v in = 3.3v internal reference voltage vs temperature
ltc3418 4 3418fb typical performance characteristics quiescent current vs input voltage input voltage (v) 2.5 0 quiescent current (a) 100 200 300 3 3.5 4 4.5 3418 g05 5 400 500 50 150 250 350 450 5.5 input voltage (v) 2.25 0 leakage current (na) 0.5 1.5 2.0 2.5 4.25 5.0 4.5 3418 g04 1.0 3.25 2.75 4.75 3.75 5.25 3.0 pfet nfet 3.5 4.0 switch leakage vs input voltage frequency vs input voltage input voltage (v) 2.25 900 frequency (khz) 920 960 980 1000 4.25 1100 1080 3418 g08 940 3.25 2.75 4.75 3.75 5.25 1020 1040 1060 temperature (c) C40 900 frequency (khz) 920 960 980 1000 1100 1040 0 40 60 3418 g07 940 1060 1080 1020 C20 20 80 100 120 v in = 3.3v frequency vs temperature frequency vs r osc r osc (k) 10 0 frequency (khz) 500 1500 2000 2500 170 4500 3418 g06 1000 90 50 210 130 250 3000 3500 4000 v in = 3.3v ef? ciency and power loss vs load current ef? ciency vs load current load current (a) 0.01 40 efficiency (%) 50 60 70 80 0.1 1 10 3418 g10 30 20 10 0 90 100 burst mode operation forced continuous v in = 3.3v v out = 2.5v ef? ciency vs load current load current (a) 0.01 40 efficiency (%) 50 60 70 80 0.1 1 10 3418 g11 30 20 10 0 90 100 3.3v 5v forced continuous v out = 2.5v ef? ciency vs load current load current (a) 0.01 40 efficiency (%) 50 60 70 80 0.1 1 10 3418 g12 30 20 10 0 90 100 3.3v 5v burst mode operation v out = 2.5v load current (a) 0.01 60 efficiency (%) power loss (mw) 80 100 0.1 1 10 3418 g09 40 50 70 90 30 20 1000 100000 100 10000 10 1 efficiency power loss v in = 3.3v v out = 2.5v t a = 25c unless otherwise noted.
ltc3418 5 3418fb typical performance characteristics load regulation peak inductor current vs burst clamp voltage v bclamp (v) 0 0 peak inductor current (a) 2 4 6 8 0.2 0.4 0.6 0.8 3418 g13 10 12 0.1 0.3 0.5 0.7 3.3v 5v load current (a) 0 C0.30 v out /v out (%) C0.25 C0.20 C0.15 C0.10 24 6 8 3418 g14 C0.05 0 13 5 7 v in = 3.3v v out = 1.8v f = 1mhz load step transient output voltage 100mv/div inductor current 5a/div 20s/div v in = 3.3v v out = 2.5v load step: 800ma to 8a 3418 g15 load step transient output voltage 100mv/div inductor current 5a/div 40s/div v in = 3.3v v out = 2.5v load step: 3a to 8a 3418 g16 burst mode operation start-up transient output voltage 100mv/div inductor current 1a/div 20s/div v in = 3.3v v out = 2.5v load: 200ma 3418 g17 output voltage 500mv/div inductor current 2a/div 1ms/div v in = 3.3v v out = 2.5v load: 8a 3418 g18 t a = 25c unless otherwise noted. pin functions sw (pins 1, 2, 11, 12, 20, 21, 30, 31): switch node connection to inductor. this pin connects to the drains of the internal main and synchronous power mosfet switches. pv in (pins 3, 4, 9, 10, 22, 23, 28, 29): power input supply. decouple these pins to pgnd with capacitors on all four corners of the package. pgood (pin 5): power good output. open-drain logic output that is pulled to ground when the output voltage is not within 7.5% of regulation point. r t (pin 6): oscillator resistor input. connecting a resistor to ground from this pin sets the switching frequency. run/ss (pin 7): run control and soft-start input. forcing this pin below 0.5v shuts down the ltc3418. in shutdown all functions are disabled drawing <1.5a of supply cur- rent. a capacitor to ground from this pin sets the ramp time to full output current. sgnd (pin 8): signal ground. all small-signal components and compensation components should connect to this ground, which in turn connects to pgnd at one point. pgnd (pins 13, 14, 15, 17, 18, 19, 32, 33, 34, 36, 37, 38): power ground. connect this pin closely to the (C) terminal of c in and c out .
ltc3418 6 3418fb block diagram pin functions v ref (pin 16): reference output. decouple this pin with a 2.2f capacitor. sv in (pin 24): signal input supply. decouple this pin to sgnd with a capacitor. v fb (pin 25): feedback pin. receives the feedback voltage from a resistive divider connected across the output. i th (pin 26): error ampli? er compensation point. the current comparator threshold increases with this control voltage. nominal voltage range for this pin is from 0.2v to 1.4v with 0.4v corresponding to the zero-sense voltage (zero current). sync/mode (pin 27): mode select and external clock synchronization input. to select forced continuous, tie to sv in . connecting this pin to a voltage between 0v and 1v selects burst mode operation with the burst clamp set to the pin voltage. track (pin 35): voltage tracking input. feedback volt- age will regulate to the voltage on this pin during start-up power sequencing. exposed pad (pin 39): the exposed pad is pgnd and must be soldered to the pcb ground for electrical connection and rated thermal performance. C + C + C + C + C + C + slope compensation recovery oscillator nmos current comparator current reverse comparator slope compensation logic error amplifier burst comparator pmos current comparator pv in voltage reference 35 track 25 v fb 5 pgood 7 run/ss run 0.74v sync/mode 0.86v 16 26 10 9 4 3 v ref i th sync/mode bclamp 8 sgnd 24 sv in + 22 1 2 11 12 20 21 30 31 23 28 29 sw 13 32 14 33 15 34 17 36 18 37 19 27 r t 6 38 pgnd 3418 bd C +
ltc3418 7 3418fb operation main control loop the ltc3418 is a monolithic, constant frequency, current mode step-down dc/dc converter. during normal opera- tion, the internal top power switch (p-channel mosfet) is turned on at the beginning of each clock cycle. current in the inductor increases until the current comparator trips and turns off the top power mosfet. the peak inductor current at which the current comparator shuts off the top power switch is controlled by the voltage on the i th pin. the error ampli? er adjusts the voltage on the i th pin by comparing the feedback signal from a resistor divider on the v fb pin with an internal 0.8v reference. when the load current increases, it causes a reduction in the feedback voltage relative to the reference. the error ampli? er raises the i th voltage until the average inductor current matches the new load current. when the top power mosfet shuts off, the synchronous power switch (n-channel mosfet) turns on until either the bottom current limit is reached or the beginning of the next clock cycle. the bottom current limit is set at C8a for force continuous mode and 0a for burst mode operation. the operating frequency is externally set by an external resistor connected between the r t pin and ground. the practical switching frequency can range from 300khz to 4mhz. overvoltage and undervoltage comparators will pull the pgood output low if the output voltage comes out of regulation by 7.5%. in an overvoltage condition, the top power mosfet is turned off and the bottom power mosfet is switched on until either the overvoltage condition clears or the bottom mosfets current limit is reached. forced continuous connecting the sync/mode pin to sv in will disable burst mode operation and force continuous current operation. at light loads, forced continuous mode operation is less ef? cient than burst mode operation, but may be desirable in some applic a t ions w her e i t is ne c e s s ar y to ke ep sw i tch - ing harmonics out of a signal band. the output voltage ripple is minimized in this mode. burst mode operation connecting the sync/mode pin to a voltage in the range of 0v to 1v enables burst mode operation. in burst mode operation, the internal power mosfets operate intermit- tently at light loads. this increases ef? ciency by minimiz- ing switching losses. during burst mode operation, the minimum peak inductor current is externally set by the voltage on the sync/mode pin and the voltage on the i th pin is monitored by the burst comparator to determine when sleep mode is enabled and disabled. when the average inductor current is greater than the load current, the voltage on the i th pin drops. as the i th voltage falls below 350mv, the burst comparator trips and enables sleep mode. during sleep mode, the top power mosfet is held off while the load current is solely supplied by the output capacitor. when the output voltage drops, the top and bottom power mosfets begin switching to bring the output back into regulation. this process repeats at a rate that is dependent on the load demand. pulse skipping operation can be implemented by connect- ing the sync/mode pin to ground. this forces the burst clamp level to be at 0v. as the load current decreases, the peak inductor current will be determined by the voltage on the i th pin until the i th voltage drops below 400mv. at this point, the peak inductor current is determined by the minimum on-time of the current comparator. if the load demand is less than the average of the minimum on-time inductor current, switching cycles will be skipped to keep the output voltage in regulation. frequency synchronization the internal oscillator of the ltc3418 can by synchronized to an external clock connected to the sync/mode pin. the frequency of the external clock can be in the range of 300khz to 4mhz. for this application, the oscill ator timing resistor should be chosen to correspond to a frequency that is 25% lower than the synchronization frequency. during synchroniza- tion, the burst clamp is set to 0v, and each switching cycle begins at the falling edge of the clock signal.
ltc3418 8 3418fb operation dropout operation when the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on-time. further reduction of the supply voltage forces the main switch to remain on for more than one cycle eventually reaching 100% duty cycle. the output voltage will then be determined by the input voltage minus the voltage drop across the internal p-channel mosfet and the inductor. low supply operation the ltc3418 is designed to operate down to an input sup- ply voltage of 2.25v. one important consideration at low input supply voltages is that the r ds(on) of the p-channel and n-channel power switches increases. the user should calculate the power dissipation when the ltc3418 is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. slope compensation and inductor peak current slope compensation provides stability in constant fre- quency architectures by preventing subharmonic oscilla- tions at duty cycles greater than 50%. it is accomplished internally by adding a compensating ramp to the inductor current signal. normally, the maximum inductor peak current is reduced when slope compensation is added. in the ltc3418, however, slope compensation recovery is implemented to keep the maximum inductor peak cur- rent constant throughout the range of duty cycles. this keeps the maximum output current relatively constant regardless of duty cycle. short-circuit protection when the output is shorted to ground, the inductor cur- rent decays very slowly during a single switching cycle. to prevent current runaway from occurring, a secondary current limit is imposed on the inductor current. if the inductor valley current increases larger than 15a, the top power mosfet will be held off and switching cycles will be skipped until the inductor current is reduced. voltage tracking some microprocessors and dsp chips need two power supplies with different voltage levels. these systems often require voltage sequencing between the core power sup- ply and the i/o power supply. without proper sequencing, latch-up failure or excessive current draw may occur that could result in damage to the processors i/o ports or the i/o ports of a supporting system device such as memory, an fpga or a data converter. to ensure that the i/o loads are not driven until the core voltage is properly biased, tracking of the core supply and the i/o supply voltage is necessary. voltage tracking is enabled by applying a ramp voltage to the track pin. when the voltage on the track pin is below 0.8v, the feedback voltage will regulate to this tracking voltage. when the tracking voltage exceeds 0.8v, control over the feedback voltage is gradually released. full release of tracking control over the feedback voltage is achieved when the tracking voltage exceeds 1.05v. voltage reference output the ltc3418 provides a 1.25v reference voltage that is capable of sourcing up to 5ma of output current. this reference voltage is generated from a linear regulator and is intended for applications requiring a low noise reference voltage. to ensure that the output is stable, the reference voltage pin should be decoupled with a minimum of 2.2f.
ltc3418 9 3418fb applications information the basic ltc3418 application circuit is shown on the front page of this data sheet. external component selection is determined by the maximum load current and begins with the selection of the operating frequency and inductor value followed by c in and c out . operating frequency selection of the operating frequency is a tradeoff between ef? ciency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequencies improves ef? ciency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. the operating frequency of the ltc3418 is determined by an external resistor that is connected between the r t pin and ground. the value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: r osc = 7.3 ? 10 10 f ? ? ? ? ? 2.5k although frequencies as high as 4mhz are possible, the minimum on-time of the ltc3418 imposes a minimum limit on the operating duty cycle. the minimum on-time is typically 80ns. therefore, the minimum duty cycle is equal to: 100 ? 80ns ? f(hz) inductor selection for a given input and output voltage, the inductor value and operating frequency determine the ripple current. the ripple current i l increases with higher v in or v out and decreases with higher inductance: i l = v out f l 1C v out v i n having a lower ripple current reduces the core losses in the inductor, the esr losses in the output capacitors and the output voltage ripple. highest ef? ciency operation is achieved at low frequency with small ripple current. this, however, requires a large inductor. a reasonable starting point for selecting the ripple current is i l = 0.4(i max ). the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below a speci? ed maximum, the inductor value should be chosen according to the following equation: l = v out f i l(max ) 1C v out v in(max ) the inductor value will also have an effect on burst mode operation. the transition from low current operation begins when the peak inductor current falls below a level set by the burst clamp. lower inductor values result in higher ripple current which causes this to occur at lower load currents. this causes a dip in ef? ciency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to increase. inductor core selection once the value for l is known, the type of inductor must be selected. actual core loss is independent of core size for a ? xed inductor value, but it is very dependent on the inductance selected. as the inductance increases, core losses decrease. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core losses and are pre- ferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that i n d u c t a n c e c o l l a p s e s a b r u p t l y w h e n t h e p e a k d e s i g n c u r r e n t is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate!
ltc3418 10 3418fb applications information different core materials and shapes will change the size/cur- rent and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy, but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price vs size requirements and any radiated ? eld/emi requirements. new designs for surface mount inductors are available from coiltronics, coilcraft, toko and sumida. c in and c out selection the input capacitance, c in , is needed to ? lter the trapezoidal wave current at the source of the top mosfet. to prevent large voltage transients from occurring, a low esr input capacitor sized for the maximum rms current should be used. the maximum rms current is given by: i rms = i out(max) v out v in v in v out ?1 this formula has a maximum at v in = 2v out , where i rms = i out / 2 . t h i s s i m p l e w o r s t - c a s e c o n d i t i o n i s c o m m o n l y u s e d for design because even signi? cant deviations do not offer much relief. note that ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. the selection of c out is determined by the effective series r e s i s t a n c e ( e s r) t h a t i s r e q u i r e d t o m i n i m i z e v o l t a g e r i p p l e and load step transients as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v out , is determined by: v out i l esr + 1 8fc ou t the output ripple is highest at maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have signi? cantly higher esr, but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic capaci- tors have excellent low esr characteristics but can have a high voltage coef? cient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to signi? cant ringing. using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v in . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. when choosing the input and output ceramic capacitors, choose the x5r or x7r dielectric formulations. these dielectrics have the best temperature and voltage charac- teristics of all the ceramics for a given value and size. output voltage programming the output voltage is set by an external resistive divider according to the following equation: v out = 0.8 1 + r2 r 1 the resistive divider allows pin v fb to sense a fraction of the output voltage as shown in figure 1.
ltc3418 11 3418fb burst clamp programming if the voltage on the sync/mode pin is less than v in by 1v, burst mode operation is enabled. during burst mode operation, the voltage on the sync/mode pin determines the burst clamp level, which sets the minimum peak induc- tor current, i burst , for each switching cycle. a graph show- ing the relationship between the minimum peak inductor current and the voltage on the sync/mode pin can be found in the typical performance characteristics section. in the graph, v burst is the voltage on the sync/mode pin. i burst can only be programmed in the range of 0a to 10a. for values of v burst less than 0.4v, i burst is set at 0a. as the output load current drops, the peak inductor currents decrease to keep the output voltage in regulation. when the output load current demands a peak inductor current that is less than i burst , the burst clamp will force the peak inductor current to remain equal to i burst regard- less of further reductions in the load current. since the average inductor current is greater than the output load current, the voltage on the i th pin will decrease. when the i th voltage drops to 350mv, sleep mode is enabled in which both power mosfets are shut off and switching action is discontinued to minimize power consumption. all circuitry is turned back on and the power mosfets begin switching again when the output voltage drops out of regulation. the value for i burst is determined by the desired amount of output voltage ripple. as the value of i burst increases, the sleep period between pulses and the output voltage ripple increase. the burst clamp voltage, v burst , can be set by a resistor divider from the v fb pin to the sgnd pin as shown in the typical application on the front page of this data sheet. pulse skipping, which is a compromise between low output voltage ripple and ef? ciency during low load current opera- tion, can be implemented by connecting the sync/mode v fb v out r1 3418 f01 r2 sgnd ltc3418 figure 1. setting the output voltage pin to ground. this sets i burst to 0a . in this condi tion, the peak inductor current is limited by the minimum on-time of the current comparator; and the lowest output voltage ripple is achieved while still operating discontinuously. during ver y light output loads, pulse skipping allows only a few switching cycles to be skipped while maintaining the output voltage in regulation. voltage tracking the ltc3418 allows the user to program how its output voltage ramps during start-up by means of the track pin. through this pin, the output voltage can be set up to either track coincidentally or ratiometrically follow another output voltage as shown in figure 2. if the voltage on the track pin is less than 0.8v, voltage tracking is enabled. during voltage tracking, the output voltage regulates to the tracking voltage through a resistor divider network. v out2 v out1 3418 f02a time output voltage v out2 v out1 3418 f02a time output voltage figure 2a. coincident tracking figure 2b. ratiometric sequencing applications information
ltc3418 12 3418fb the output voltage during tracking can be calculated with the following equation: v out = v track 1 + r2 r 1 ,v track < 0.8v t2, fv out2 trackfltc3418 3.tf fv out1 . t 2, track 1.05vf. tltc3418ztrack track0.8v. ,track f f. ,f f. v out2 1.32v out1 ,f r4 = r3 v out2 v trac k C1 v track 1.05v top mosfet turn-on is locked to the falling edge of the external frequency source. the synchronization frequency range is 300khz to 4mhz. synchronization only occurs if the external frequency is greater than the frequency set by the external resistor. because slope compensation is generated by the oscillators rc circuit, the external frequency should be set 25% higher than the frequency set by the external resistor to ensure that adequate slope compensation is present. soft-start the run/ss pin provides a means to shut down the ltc3418 as well as a timer for soft-start. pulling the run/ ss pin below 0.5v places the ltc3418 in a low quiescent current shutdown state (i q < 1.5a). the ltc3418 contains a soft-start clamp that can be set externally with a resistor and capacitor on the run/ss pin as shown in typical application on the front page of this data sheet. the soft-start duration can be calculated by using the following formula: t ss = r ss ?c ss ?in v in v in ?1. 8 v seconds ? ? ? ? ef? ciency considerations the ef? ciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the ef? ciency and which change would produce the most improvement. ef? ciency can be expressed as: ef? ciency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses: v in quiescent current and i 2 r losses. the v in quiescent current loss dominates the ef? ciency loss at very low load currents whereas the i 2 r loss dominates the ef? ciency loss at medium to high load currents. in a typical ef? ciency plot, the ef? ciency curve at very low r2 r4 r1 r3 v out2 (master) track pin v fb(master) pin 3418 f03 figure 3 frequency synchronization the ltc3418s internal oscillator can be synchronized to an external clock signal. during synchronization, the applications information
ltc3418 13 3418fb load currents can be misleading since the actual power lost is of no consequence. 1. the v in quiescent current is due to two components: the dc bias current as given in the electrical charac- teristics and the internal main switch and synchronous switch gate charge currents. the gate charge current results from switching the gate capacitance of the internal power mosfet switches. each time the gate is switched from high to low to high again, a packet of charge dq moves from v in to ground. the resulting dq/dt is the current out of v in that is typically larger t h a n t h e d c b i a s c ur r e n t . in c o n t i nu o u s mo d e, i gatechg = f(q t + q b ) where q t and q b are the gate charges of the internal top and bottom switches. both the dc bias and gate charge losses are proportional to v in and thus their effects will be more pronounced at higher supply voltages. 2. i 2 r losses are calculated from the resistances of the internal switches, r sw , and external inductor r l . in continuous mode the average output current ? owing through inductor l is chopped between the main switch and the synchronous switch. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on)top )(dc) + (r ds(on)bot )(1 C dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance character- istics curves. thus, to obtain i 2 r losses, simply add r sw to r l and multiply the result by the square of the average output current. other losses including c in and c out esr dissipative losses and inductor core losses generally account for less than 2% of the total loss. thermal considerations in most applications, the ltc3418 does not dissipate much heat due to its high ef? ciency. but, in applications where the ltc3418 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. if the junction temperature reaches approximately 150c, both power switches will be turned off and the sw node will become high impedance. to avoid the ltc3418 from exceeding the maximum junc- tion temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the temperature rise is given by: t r = (p d )( ja ) where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient temperature. for the 38-lead 5mm 7mm qfn package, the ja is 34c/w. the junction temperature, t j , is given by: t j = t a + t r where t a is the ambient temperature. n o t e t h a t a t h i g h e r s u p p l y v o l t a g e s , t h e j u n c t i o n t e m p e r a t u r e is lower due to reduced switch resistance (r ds(on) ). checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to i load (esr), where esr is the effective series resistance of c out . i load also begins to charge or discharge c out generating a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the i th pin external components and output capacitor shown in the typical application on the front page of this data sheet will provide adequate compensa- tion for most applications. design example as a design example, consider using the ltc3418 in an application with the following speci? cations: v in = 3.3v, v out = 2.5v, i out(max) = 8a, i out(min) = 200ma, f = 1mhz. applications information
ltc3418 14 3418fb because ef? ciency is important at both high and low load current, burst mode operation will be utilized. first, calculate the timing resistor: r osc = 7.3 ? 10 10 1? 10 6 ? 2.5k = 70.5k use a standard value of 69.8k. next, calculate the inductor value for about 40% ripple current: l = 2.5v 1m h z () 3.2a ( ) 1C 2.5v 3.3 v = 0.19 h u0.2h f i l = 2.5v 1m h z () 0.2 h ( ) 1C 2.5v 3.3 v = 3.03a c out esr f f., 100. c in zff i rms = 8a () 2.5v 3.3 v 3.3v 2.5 v C 1 = 3.43a rms decoupling the pv in and sv in pins with four 100f capaci- tors is adequate for this application. the burst clamp and output voltage can now be pro- grammed by choosing the values of r1, r2 and r3. the voltage on the mode pin will be set to 0.67v by the resistor divider consisting of r2 and r3. a burst clamp voltage of 0.67v will set the minimum inductor current, i burst , to approximately 1.2a. pv in pv in pv in pv in pv in pv in pv in pv in sv in track pgood run/ss i th r t sgnd pgnd pgnd pgnd pgnd 1 2 11 12 20 21 30 31 25 27 38 37 36 34 33 32 19 18 16 3 4 9 10 22 23 28 29 24 35 5 7 26 6 8 13 14 15 17 sw sw sw sw sw sw sw sw v fb sync/mode pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd v ref ltc3418 l1 0.2h c1 22pf x7r c out 100f 5 c ref 2.2f x7r c in 100f 4 v in 3.3v v out 2.5v 8a r1 432k r pg 100k r ss 2.2m c ss 1000pf x7r c ith 820pf x7r r ith 7.5k r svin 100 r osc 69.8k r2 33.2k r3 169k v ref c1 47pf x7r 3418 f04 c in , c out : avx 18126d107mat l1: toko fdv0620-r20m c svin 1f x7r figure 4. 2.5v, 8a regulator at 1mhz, burst mode operation applications information
ltc3418 15 3418fb applications information if we set the sum of r2 and r3 to 200k, then the following equations can be solved. rr k r r v v 2 3 200 1 2 3 0 8 067 += += . . the two equations shown above result in the following values for r2 and r3: r2 = 33.2k, r3 = 169k. the value of r1 can now be determined by solving the equation: 1 1 202 2 25 0 8 1 430 += = r k v v rk . . . a value of 432k will be selected for r1. figure 4 shows the complete schematic for this design example. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3418. check the following in your layout. 1. a ground plane is recommended. if a ground plane layer is not used, the signal and power grounds should be segregated with all small-signal components returning to the sgnd pin at one point which is then connected to the pgnd pin close to the ltc3418. 2. connect the (+) terminals of the input capacitor(s), c in , as close as possible to the pv in and pgnd pins at all four corners of the package. these capacitors provide the ac current into the internal power mosfets. 3. keep the switching node, sw, away from all sensitive small-signal nodes. 4. flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power components. you can connect the copper areas to any dc net (pv in , sv in , v out , pgnd, sgnd or any other dc rail in your system). 5. connect the v fb pin directly to the feedback resistors. the resistor divider must be connected between v out and sgnd. 6. to minimize switching noise coupling to sv in , place an optional local ? lter between sv in and pv in . most designs do not require this ? lter. figure 5. ltc3418 layout diagram bottom layer top layer
ltc3418 16 3418fb typical applications 3.3v, 8a step-down regulator synchronized to 1.25mhz pv in pv in pv in pv in pv in pv in pv in pv in sv in track pgood run/ss i th r t sgnd pgnd pgnd pgnd sync/mode 1 2 11 12 20 21 30 31 25 16 38 37 36 34 33 32 19 18 17 3 4 9 10 22 23 28 29 24 35 5 7 26 6 8 13 14 15 27 sw sw sw sw sw sw sw sw v fb v ref pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd ltc3418 l1 0.33h c1 1000pf x7r c out 100f 3 c in 100f 2 c svin 1f x7r v in 5v v out 3.3v 8a r1 6.34k r pg 100k r ss 2.2m c ss 1000pf x7r c ith 2200pf x7r r ith 2k r svin 100 r osc 69.8k r2 2k c1 47pf x7r 1.25mhz clock c ref 2.2f x7r v ref 3418 ta02 c in , c out : tdk c3225x5r0j107m l1: vishay dale ihlp-2525cz-01 pv in pv in pv in pv in pv in pv in pv in pv in sv in track sync/mode pgood run/ss i th r t sgnd pgnd pgnd pgnd 1 2 11 12 20 21 30 31 25 16 38 37 36 34 33 32 19 18 17 3 4 9 10 22 23 28 29 24 35 27 5 7 26 6 8 14 15 13 sw sw sw sw sw sw sw sw v fb v ref pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd ltc3418 l1 0.2h c1 1000pf x7r c out 100f 3 c in 100f 4 v in 3.3v v out 1.2v 8a r1 1k r pg 100k r ss 2.2m c ss 1000pf x7r c ith 2200pf x7r r ith 4.99k r svin 100 r osc 30.1k r2 2k c1 47pf x7r c ref 2.2f x7r c svin 1f x7r v ref 3418 ta03 c in , c out : avx 12106d107mat l1: cooper fp3-r20 1.2v, 8a step-down regulator at 2mhz, forced continuous mode
ltc3418 17 3418fb typical applications 1.8v, 8a step-down regulator with tracking track pv in pv in pv in pv in pv in pv in pv in pv in sv in pgood sync/mode run/ss i th r t sgnd pgnd pgnd pgnd 1 2 11 12 20 21 30 31 25 16 38 37 36 34 33 32 19 18 17 35 3 4 9 10 22 23 29 28 24 5 27 7 26 6 8 13 14 15 sw sw sw sw sw sw sw sw v fb v ref pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd ltc3418 l1 0.2h c1 1000pf x7r c out 100f 2 c in 100f 4 c svin 1f x7r v in 3.3v v out 1.8v 8a r1 2.55k r ss 2.2m r pg 100k c ss 1000pf x7r c ith 2200pf x7r r ith 3.32k r svin 100 r osc 69.8k r2 2k c1 47pf x7r c ref 2.2f x7r v ref 3418 ta04 c in , c out : tdk c3225x5r0j107m l1: vishay dale ihlp-2525cz-01 r4 2k r3 2.55k 2.5v i/o supply
ltc3418 18 3418fb typical applications 1.8v, 16a step-down regulator pv in pv in pv in pv in pv in pv in pv in pv in sv in track pgood run/ss i th r t sgnd pgnd pgnd pgnd sync/mode 1 2 11 12 20 21 30 31 25 38 37 36 34 33 32 19 18 17 16 3 4 9 10 22 23 28 29 24 35 5 7 26 6 8 13 14 15 27 sw sw sw sw sw sw sw sw v fb pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd v ref ltc3418 l1 0.2h c2 1000pf x7r c out 100f 4 c in1 100f 4 c svin1 1f x7r v in 3.3v v out 1.8v 16a r1 2.55k r2 2k r pg1 100k r ss1 2.2m c ss1 1000pf x7r c1a 47pf x7r c ith 2200pf x7r c ref1 2.2mf x7r r ith 2k r osc1 59k r svin1 100w c svin2 1f x7r r svin2 100 c ref2 2.2f x7r c1b 47pf x7r 3418 ta06 pv in pv in pv in pv in pv in pv in pv in pv in sv in track pgood run/ss i th r t sgnd pgnd pgnd pgnd sync/mode 1 2 11 12 20 21 30 31 25 38 37 36 34 33 32 19 18 17 16 3 4 9 10 22 23 28 29 24 35 5 7 26 6 8 13 14 15 27 sw sw sw sw sw sw sw sw v fb pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd v ref ltc3418 l2 0.2h c3 1000pf x7r c in2 100f 4 r3 2.55k r4 2k c in1 , c in2 , c out : tdk c3225x5r0j107m l1, l2: vishay dale ihlp-2525cz-01 r pg2 100k r ss2 2.2m c ss2 1000pf x7r r osc2 69.8k
ltc3418 19 3418fb information furnished by linear technology corpor ation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- t i o n t h a t t h e i n t e r c o n n e c t i o n o f i t s c i r c u i t s a s d e s c r i b e d h e r e i n w i l l n o t i n f r i n g e o n e x i s t i n g p a t e n t r i g h t s . package description uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701) 5.00 p 0.10 note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 37 1 2 38 bottom viewexposed pad 5.50 ref 5.15 0.10 7.00 p 0.10 0.75 p 0.05 r = 0.125 typ r = 0.10 typ 0.25 p 0.05 (uh) qfn ref c 1107 0.50 bsc 0.200 ref 0.00 C 0.05 recommended solder pad layout apply solder mask to areas that are not soldered 3.00 ref 3.15 0.10 0.40 p 0.10 0.70 p 0.05 0.50 bsc 5.5 ref 3.00 ref 3.15 0.05 4.10 p 0.05 5.50 p 0.05 5.15 0.05 6.10 p 0.05 7.50 p 0.05 0.25 p 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 s 45 o chamfer
ltc3418 20 3418fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt 0908 rev b ? printed in the usa related parts typical application part number description comments lt1616 500ma (i out ), 1.4mhz, high ef? ciency step-down dc/dc converter 90% ef? ciency, v in : 3.6v to 25v, v out = 1.25v, i q = 1.9ma, i sd < 1a, thinsot package lt1676 450ma (i out ), 100khz, high ef? ciency step-down dc/dc converter 90% ef? ciency, v in : 7.4v to 60v, v out = 1.24v, i q = 3.2ma, i sd < 2.5a, s8 package lt1765 25v, 2.75a (i out ), 1.25mhz, high ef? ciency step-down dc/dc converter 90% ef? ciency, v in : 3v to 25v, v out = 1.2v, i q = 1ma, i sd < 15a, s8, tssop16e packages ltc1879 1.20a (i out ), 550khz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.7v to 10v, v out = 0.8v, i q = 15a, i sd < 1a, tssop16 package ltc3405/ltc3405a 300ma (i out ), 1.5mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.75v to 6v, v out = 0.8v, i q = 20a, i sd < 1a, thinsot package ltc3406/ltc3406b 600ma (i out ), 1.5mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out = 0.6v, i q = 20a, i sd < 1a, thinsot package ltc3407 dual 600ma (i out ), 1.5mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out = 0.6v, i q = 40a, i sd < 1a, ms package ltc3411 1.25a (i out ), 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out = 0.8v, i q = 60a, i sd < 1a, ms package ltc3412 2.5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.5v to 5.5v, v out = 0.8v i q = 60a, i sd < 1a, tssop16e package ltc3413 3a (i out sink/source), 2mhz, monolithic synchronous regulator for ddr/qdr memory termination 90% ef? ciency, v in : 2.25v to 5.5v, v out = v ref /2, i q = 280a, i sd < 1a, tssop16e package ltc3414 4a (i out ), 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 64a, i sd < 1a, tssop20e package ltc3416 4a (i out ), 4mhz, synchronous step-down dc/dc converter with tracking 95% ef? ciency, v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 300a, i sd < 1a, tssop20e package low noise 1.5v, 8a step-down regulator pv in pv in pv in pv in pv in pv in pv in pv in sv in track pgood run/ss i th r t sync/mode sgnd pgnd pgnd pgnd 1 2 11 12 20 21 30 31 25 16 38 37 36 34 33 32 19 18 17 3 4 9 10 22 23 28 29 24 35 5 7 26 6 27 8 13 14 15 sw sw sw sw sw sw sw sw v fb v ref pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd ltc3418 l1 0.2h c1 1000pf x7r c out 100f 3 c in 100f 4 c svin 1f x7r v in 2.5v v out 1.5v 8a r1 1.78k r pg 100k r ss 2.2m c ss 1000pf x7r c ith 2200pf x7r r ith 3.32k r svin 100 r osc 69.8k r2 2k c1 47pf x7r c ref 2.2f x7r v ref 3418 ta05 c in , c out : tdk c3225x5r0j107m l1: vishay dale ihlp-2525cz-01

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